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| White Electronic Designs W72M64VK-XBX 2Mx64 3.3V Simultaneous Operation Flash Multi-Chip Package FEATURES Access Times of 90, 100, 120ns Packaging * 159 PBGA, 13x22mm - 1.27mm pitch 1,000,000 Erase/Program Cycles Sector Architecture * Bank 1 (4Mb): eight 4K word, eight 32K word * Bank 2 (12Mb): twenty-four 32K word * Bank 3 (12Mb): twenty-four 32K word * Bank 4 (4Mb): eight 32K word Bottom boot block Zero Power Operation Organized as 2Mx64 or 2x2Mx32 Commercial, Industrial and Military Temperature Ranges 3.3 Volt for Read and Write Operations Simultaneous Read/Write Operation: * Data can be continuously read from one bank while executing erase/program functions in another bank * Zero latency between read and write operations Erase Suspend/Resume * Suspends erase operations to allow programming in same bank Data# Polling and Toggle Bits * Provides a software method of detecting the status of program or erase cycles This product is subject to change without notice. Note: For programming information refer to Flash Programming W72M64V-XBX Application Note. Unlock Bypass Program command * Reduces overall programming time when issuing multiple program command sequences Ready/Busy# output (RY/BY#) * Hardware method for detecting program or erase cycle completion Hardware reset pin (RESET#) * Hardware method of resetting the internal state machine to the read mode WP#/ACC input pin * Write protect (WP#) function allows protection two outermost boot sectors, regardless of sector protect status * Acceleration (ACC) function accelerates program timing Sector Protection * Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector * Temporary Sector Unprotect allows changing data in protected sectors in-system April 2005 Rev. 0 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W72M64VK-XBX FIGURE 1: PIN CONFIGURATION FOR W72M64V-XBX Top View Pin Description 1 A B C D E F G H J K L M N P R T VCC 2 GND 3 GND 4 GND 5 VCC 6 VCC 7 GND 8 GND 9 10 GND VCC GND DQ41 WE3# VCC DQ57 DNU WE4# VCC VCC VCC DQ33 DQ43 DQ45 DQ47 DQ49 DQ59 DQ61 DQ63 VCC VCC DQ40 DQ35 DQ37 DQ39 DQ56 DQ51 DQ53 DQ55 VCC DQ0-63 A0-20 WE1-4# CS1-4# OE# RESET# WP#/ACC RY/BY# VCC GND DNU VCC DQ32 DQ42 DQ44 DQ46 DQ48 DQ58 DQ60 DQ62 VCC GND CS3# DQ34 DQ36 DQ38 CS4# DQ50 DQ52 DQ54 GND GND OE# A0 DNU* VCC A12 A16 DNU* A20 GND Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Hardware Reset Hardware Write Protect/Acceleration Ready/Busy Output Power Supply Ground Do Not Use GND A2 WP#/ACC A11 GND VCC A7 A10 A15 GND* GND A3 A6 A9 VCC GND A1 RESET# A13 GND GND A4 A17 RY/BY# GND A14 A5 A18 A8 GND GND DQ17 WE2# DQ29 DNU DQ9 DQ4 WE1# A19 GND VCC DQ24 DQ19 DQ21 DQ31 DQ1 DQ11 DQ6 DQ15 VCC VCC DQ16 DQ26 DQ28 DQ23 DQ8 DQ3 DQ13 DQ7 VCC VCC CS2# DQ18 DQ20 DQ30 DQ0 DQ10 DQ5 DQ14 VCC VCC VCC DQ25 DQ27 DQ22 CS1# DQ2 DQ12 GND VCC VCC GND GND GND VCC VCC GND GND GND VCC * Ball G8 is reserved for A21 and ball G4 is reserved for A22 on W78M64V-XSBX. WE1# Block Diagram WE2# CS2# WE3# CS3# WE4# CS4# CS1# RY/BY# RESET# OE# A0-20 2M x 16 2M x 16 2M x 16 2M x 16 VCC BYTE# BYTE# BYTE# BYTE# WP#/ACC DQ0-15 DQ16-31 DQ32-47 DQ48-63 April 2005 Rev. 0 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Operating Temperature Supply Voltage Range (VCC) Signal Voltage Range Storage Temperature Range Endurance (write/erase cycles) -55 to +125 -0.5 to +4.0 -0.5 to Vcc +0.5 -55 to +150 1,000,000 min. Unit C V V C cycles W72M64VK-XBX CAPACITANCE TA = +25C, F = 1.0MHz Parameter WE1-4# capacitance CS1-4# capacitance Data I/O capacitance Address input capacitance RESET# capacitance RY/BY# capacitance OE# capacitance Symbol CWE CCS CI/O CAD CRS CRB COE Max 8 8 10 30 26 26 32 Unit pF pF pF pF pF pF pF NOTES: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. This parameter is guaranteed by design but not tested. RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Operating Temp. (Mil.) Operating Temp. (Ind.) Symbol VCC TA TA Min 3.0 -55 -40 Max 3.6 +125 +85 Unit V C C Parameter Pattern Data Retention Time DATA RETENTION Test Conditions 150C 125C Min 10 20 Unit Years Years DC CHARACTERISTICS - CMOS COMPATIBLE VCC = 3.3V 0.3V, -55C TA +125C Parameter Input Leakage Current Output Leakage Current VCC Active Current for Read (1) VCC Active Current for Program or Erase (2,3) VCC Standby Current (2) Automatic Sleep Mode (2,4,5) VCC Active Read-While-Program Current (1,2) VCC Active Program-While-Erase Current (1,2) VCC Active Program-While-Erase-Suspended Current (2,5) ACC Accelerated Program Current Input Low Voltage Input High Voltage Voltage for WP#/ACC Sector Protect/Unprotect and Program Acceleration Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage (5) Symbol ILI ILO ICC1 ICC2 ICC3 ICC5 ICC6 ICC7 ICC8 IACC VIL VIH VHH VID VOL VOH1 VLKO Conditions VCC = 3.6V, VIN = GND to VCC VCC = 3.6V, VOUT = GND to VCC CS# = VIL#, OE = VIH, f = 5MHz CS# = VIL#, OE = VIH, WE# = VIL CS# = RESET# = VCC 0.3V VIH = VCC 0.3V; VIL = VSS 0.3V CS# = VIL#, OE = VIH CS# = VIL#, OE = VIH CS# = VIL#, OE = VIH CS# = VIL#, OE = VIH ACC Pin VCC Pin VCC = min VCC = 3.0V + 0.3V VCC = 3.0V + 0.3V IOL = 4.0 mA, VCC = 3.0V IOH = -2.0 mA, VCC = 3.0V Min -10 -10 Max 10 10 65 120 400 400 180 180 140 40 120 0.8 VCC + 0.3 9.5 12.5 0.45 2.5 Unit A A mA mA A A mA mA mA mA V V V V V V V -0.5 2.1 8.5 8.5 2.55 2.3 NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz). The frequency component typically is less than 8 mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCC MAX 3. ICC active while Embedded Algorithm (program or erase) is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30ns. 5. Not tested. April 2005 Rev. 0 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs VCC = 3.3V 0.3V, -55C TA +125C Parameter Write Cycle Time (3) Write Enable Setup Time Chip Select Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Chip Select Pulse Width High (3) Duration of Word Programming Operation (1) Sector Erase Time (2) Read Recovery Time Before Write (3) Chip Programming Time (4) Symbol tAVAV tWLEL tELEH tAVWL tDVEH tEHDX tELAX tEHEL tWHWH1 tWHWH2 tGHEL tWC tWS tCP tAS tDS tDH tAH tCPH Min 90 0 35 0 45 0 45 30 -90 Max Min 100 0 45 0 45 0 45 30 -100 Max W72M64VK-XBX AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS - CS# CONTROLLED -120 Min 120 0 50 0 50 0 50 30 Max ns ns ns ns ns ns ns ns s sec ns sec Unit 300 5 0 42 0 300 5 0 42 300 5 42 NOTES: 1. Typical value for tWHWH1 is 7s. 2. Typical value for tWHWH2 is 0.4 sec. 3. Guaranteed by design, but not tested. 4. Typical value is 36 sec. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. FIGURE 2 AC Test Circuit IOL Current Source AC Test Conditions Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level Output Timing Reference Level VZ 1.5V (Bipolar Supply) Typ VIL = 0, VIH = 2.5 5 1.5 1.5 Unit V ns V V D.U.T. CEFF = 50 pf Current Source IOH Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75W. VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. April 2005 Rev. 0 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs VCC = 3.3V 0.3V, -55C TA +125C Parameter Write Cycle Time (3) Chip Select Setup Time (3) Write Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Write Enable Pulse Width High (3) Duration of Byte Programming Operation (1) Sector Erase (2) Read Recovery Time before Write (3) VCC Setup Time Chip Programming Time (4) Address Setup Time to OE# low during toggle bit polling Write Recovery Time from RY/BY# (3) Program/Erase Valid to RY/BY# Symbol tAVAV tELWL tWLWH tAVWL tDVWH tWHDX tWLAX tWHWL tWHWH1 tWHWH2 tGHWL tVCS tWC tCS tWP tAS tDS tDH tAH tWPH Min 90 0 35 0 45 0 45 30 -90 Max Min 100 0 50 0 50 0 50 30 -100 Max W72M64VK-XBX AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS - WE# CONTROLLED -120 Min 120 0 50 0 50 0 50 30 Max ns ns ns ns ns ns ns ns s sec ns s sec ns ns ns Unit 300 5 0 50 42 tASO tRB tBUSY 15 0 90 15 0 90 0 50 300 5 0 50 42 15 0 90 300 5 42 NOTES: 1. Typical value for tWHWH1 is 7s. 2. Typical value for tWHWH2 is 0.4 sec. 3. Guaranteed by design, but not tested. 4. Typical value is 36 sec. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. AC CHARACTERISTICS - READ-ONLY OPERATIONS VCC = 3.3V 0.3V, -55C TA +125C Parameter Read Cycle Time (1) Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Select High to Output High Z Output Enable High to Output High Z Output Hold from Addresses, CS# or OE# Change, Whichever occurs first Output Enable Hold Time (1) Read Toggle and Data# Polling 1. Guaranteed by design, not tested. Symbol Min tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tRC tACC tCE tOE tDF tDF tOH tOEH 0 0 10 90 -90 Max 90 90 40 20 20 0 0 10 Min 100 -100 Max 100 100 40 20 20 0 0 10 Min 120 -120 Max Unit ns 120 120 50 20 20 ns ns ns ns ns ns April 2005 Rev. 0 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W72M64VK-XBX FIGURE 3: AC WAVEFORMS FOR READ OPERATIONS tRC Addresses tACC CS# tDF OE# tOEH WE# tCE tOE Addresses Stable tOH High Z Outputs High Z Output Valid RESET# RY/BY# OV April 2005 Rev. 0 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W72M64VK-XBX AC CHARACTERISTICS - HARDWARE RESET (RESET#) Parameter RESET# Pin Low (During Embedded Algorithms) to Read Mode (1) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (1) RESET# Pulse Width RESET# High Time Before Read (1) RESET# Low to Standby Mode (1) NOTE: 1. Not tested. Symbol Min tready tready tRP tRH tRPD 500 50 20 -90 Max 20 500 500 50 20 Min -100 Max 20 500 500 50 20 Min -120 Max 20 500 Unit s ns ns ns s FIGURE 4: RESET TIMINGS NOT DURING EMBEDDED ALGORITHMS RY/BY# CS#, OE# tRH RESET# tRP tReady FIGURE 5: RESET TIMINGS DURING EMBEDDED ALGORITHMS tReady RY/BY# CS#, OE# RESET# tRP April 2005 Rev. 0 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs FIGURE 6: PROGRAM OPERATIONS W72M64VK-XBX tWC Addresses 555h tAS PA tAS PA PA CS# tCH OE# tWP WE# tCS tWPH tDH tWHWH1 tDS Data A0h PD tBUSY Status DOUT tRB RY/BY# VCC tVCS NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. DOUT is the output of the data written to the device. 4. Figure indicates last two bus cycles of four bus cycle sequence. April 2005 Rev. 0 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W72M64VK-XBX FIGURE 7: ACCELERATED PROGRAM TIMING DIAGRAM VHH WP#/ACC VIL or VIH tVHH tVHH VIL or VIH FIGURE 8: CHIP/SECTOR ERASE OPERATION TIMINGS tWC Addresses 2AAh tAS SA 555h for chip erase VA tAH VA CS# OE# tWP WE# tCS tDS tCH tWPH tDH tWHWH2 30h 10 for Chip Erase Data 55h In Progress tBUSY Complete tRB RY/BY# tVCS VCC NOTES: 1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data April 2005 Rev. 0 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W72M64VK-XBX FIGURE 9: BACK TO BACK READ/WRITE CYCLE TIMINGS tWC Addresses Valid PA tAH tACC CS# tCE tOE OE# tWP WE# tWPH tDS Data tDH Valid In tSR/W tOEH tGHWL tDF tOH Valid Out Valid In Valid In tCP tCPH tRC Valid RA tWC Valid PA tWC Valid PA WE# Controlled Write Cycle Read Cycle CS# Controlled Write Cycle FIGURE 10: DATA POLLING TIMINGS (DURING EMBEDDED ALGORITHMS) tRC Addresses VA tACC tCE tCH OE# tOEH WE# tOH DQ7 Complement Complement True Valid Data High Z tDF tOE VA VA CS# DQ0-DQ6 tBUSY RY/BY# Status Data Status Data True Valid Data High Z NOTE: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. April 2005 Rev. 0 10 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W72M64VK-XBX FIGURE 11: TOGGLE BIT TIMINGS (DURING EMBEDDED ALGORITHMS) tAHT Addresses tAS tAHT tASO CS# tOEH WE# tOEPH OE# tDH DQ6/DQ2 Valid Data Valid Status (First Read) RY/BY# tOE Valid Status (Second Read) Valid Status (Stops Toggling) Valid Data tCEPH NOTE: VA = Valid address, not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. FIGURE 12: DQ2 Vs. DQ6 Enter Embedded Erasing Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete WE# Erase Suspend Read DQ6 DQ2 NOTE: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CS# to toggle DQ2 and DQ6. April 2005 Rev. 0 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W72M64VK-XBX FIGURE 13: SECTOR/SECTOR BLOCK PROTECT AND UNPROTECT TIMING DIAGRAM VID RESET# VIH SA, A6, A1, A0 Valid* Sector/Sector Block Protect or Unprotect Valid* Verify 40h Valid* Data 60h 60h Status Sector/Sector Block Protect: 150 s Sector/Sector Block Unprotect: 15 ms 1 s CS# WE# OE# NOTE: VA = Valid address, not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. AC CHARACTERISTICS - ALTERNATE CS# CONTROLLED ERASE AND PROGRAM OPERATIONS Parameter JEDEC tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH1 tWHWH2 Std tWC tAS tAH tDS tDH tGHEL TWS tWH tCP tCPH tWHWH1 tWHWH1 tWHWH2 Description Write Cycle Time (1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CS# Pulse Width CS# Pulse Width High Programming Operation Accelerated Programming Operation Sector Erase Operation Min Min Min Min Min Min Min Min Min Min Typ Typ Typ 90 90 0 45 45 0 0 0 0 35 30 7 4 0.4 Speed Options 100 100 0 45 45 0 0 0 0 45 30 7 4 0.4 120 120 0 50 50 0 0 0 0 50 30 7 4 0.4 Unit ns ns ns ns ns ns ns ns ns ns s s sec NOTE: 1. Not tested. April 2005 Rev. 0 12 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W72M64VK-XBX FIGURE 14: ALTERNATE CS# CONTROLLED WRITE (ERASE/PROGRAM) OPERATION TIMINGS 555 for Program 2AA for Erase PA for Program SA for Sector Erase 555 for Chip Erase Data# Polling Addresses tWC tWH WE# tGHEL OE# tCP CS# tWS tDS tDH Data tHR A0 for Program 55 for Erase PD for Program 30 for Sector Erase 10 for Chip Erase PA tAS tAH tWHWH1 OR 2 tCPH tBUSY DQ7# DOUT RESET# RY/BY# NOTES: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7 is the complement of the data written to the device. DOUT is the data written to the device. April 2005 Rev. 0 13 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs PACKAGE: 159 PBGA Bottom View 159 X O 0.762 (0.030) NOM W72M64VK-XBX 10 9 8 7 6 5 4 3 2 1 A B C 19.05 (0.750) NOM 1.27 (0.050) NOM D E F G H J K L M N P R T 22.1 (0.870) MAX 1.27 (0.050) NOM 11.43 (0.450) NOM 0.61 (0.024) NOM 2.03 (0.080) MAX 13.1 (0.516) MAX ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES. April 2005 Rev. 0 14 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs PACKAGE: 159 PBGA W72M64VK-XBX W 7 2M64 V K XXX B X WHITE ELECTRONIC DESIGNS CORP.: Flash: Organization, 2M x 64: User Configurable as 2 x 2M x 32 3.3V Power Supply: Internal Bank Architecture: K = 4 bank architecture per 2Mx16 die Access Time (ns): 90 = 90ns 100 = 100ns 120 = 120ns Package Type: B = 159 Plastic BGA, 13mm x 22mm Device Grade: M = Military Screened I = Industrial C = Commercial -55C to +125C -40C to +85C 0C to +70C April 2005 Rev. 0 15 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Document Title 2M x 64 Simultaneous Operation Flash Multi-Chip Package W72M64VK-XBX Revision History Rev # Rev 0 History Initial Release Release Date April 2005 Status Final April 2005 Rev. 0 16 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com |
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